The present invention relates in general to the field of integrated circuit packages and more specifically to substantially flat integrated circuit packages having multiple slots around the perimeter of the substrate for wire bonding and attachment of a silicon chip and having a ball grid array disposed on the substrate internal of the multiple slots.
Without limiting the scope of the invention, its background is described in connection with integrated circuit packages, as an example.
Heretofore, in this field, integrated circuits have been formed on semiconductor wafers. The wafers are separated into individual chips and the individual chips are then handled and packaged. The packaging process is one of the most critical steps in the integrated circuit fabrication process, both from the point of view of cost and of reliability. Specifically, the packaging cost can easily exceed the cost of the integrated circuit chip and the majority of device failures are packaging related.
The integrated circuit must be packaged in a suitable media that will protect it in subsequent manufacturing steps and from the environment of its intended application. Wire bonding and encapsulation are the two main steps in the packaging process. Wire bonding connects the leads from the chip to the terminals of the package. The terminals allow the integrated circuit package to be connected to other components. Following wire bonding, encapsulation is employed to seal the surfaces from moisture and contamination and to protect the wire bonding and other components from corrosion and mechanical shock.
Conventionally, the packaging of integrated circuits has involved attaching an individual chip to a lead frame, where, following wire bonding and encapsulation, designated parts of the lead frame become the terminals of the package. The packaging of integrated circuits has also involved the placement of chips on a flexible board where, following adhesion of the chip to the surface of the flexible board and wire bonding, an encapsulant is placed over the chip and the adjacent flexible board to seal and protect the chip and other components.
Unfortunately, current methods for encapsulating silicon chips have led to various problems, including cracking between the encapsulation material and the integrated circuit components, as well as high failure rates due to the multi-step nature of the process. Cracking has plagued the industry because of differences in the coefficient of thermal expansion of the different components, for example, between the soldering materials at the different interfaces and between metallic and non-metallic components. Cracking is also frequent between the silicon wafer and the encapsulation materials, usually epoxies, due to the extreme variations in temperature in various environments and between periods of operation and non-operation.
Even if the encapsulated silicon chip is successfully assembled into a working integrated circuit, another problem is commonly encountered. Once the silicon chip is encapsulated it is typically surface mounted using radiant heat or vapor saturated heating. This process, however, can lead to poor coplanarity due to uneven reflow, leading to integrated circuit failure.
Therefore, a need has arisen for an integrated circuit package and a process for producing an integrated circuit package that provides for minimizing the size of integrated circuit packages. A need has also arisen for an integrated circuit package that allows for wire bonding of the silicon chip to the printed circuit board around the perimeter of the printed circuit board while providing maximum protection to the critical components of the integrated circuit package. Also, a need has arisen for an integrated circuit package that utilizes the surface area toward the center of the printed circuit board for attachment of a high density ball grid array. Finally, a need has arisen for an integrated circuit package that solves the problem caused by the differences in thermal expansion of the packaging materials and does not require extensive encapsulation.
The present invention disclosed herein comprises an integrated circuit package that utilizes slots around the perimeter of the substrate for wire bonding the silicon chip to the substrate. The integrated circuit package of the present invention also utilizes the region of the printed circuit board inside the slots for locating a high density ball grid array. The present invention reduced the differences in the coefficient of thermal expansion of the packaging components by having a substrate with multiple opening filled with potting material.
The integrated circuit package comprises a substrate having two or more openings disposed proximate the perimeter of the substrate, first and second surfaces and an outline. A plurality of routing strips are integral with the substrate. A plurality of pads are centrally disposed on the first surface, at least one of the pads being electrically connected with at least one of the routing strips. A chip is adhered to the second surface of the substrate. The chip has an outline that is less than the outline of the substrate. The chip has at least one bonding pad, which serves to provide electrical connections to the substrate. Wire bonding electrically connects the bonding pad to the routing strips through the openings on the substrate. The wire bonding is protected from the environment by a potting material that is disposed within the openings in the substrate.
The chip is adhered to the substrate by the potting material that may be, for example, polyimide. Alternatively, the chip may be adhered by an adhesive layer, such as a polyimide adhesive layer or an adhesive epoxy tape. The epoxy can either be coated on the surface of the substrate or the chip prior to assembly.
Solder balls are disposed on the pads of the first surface of the substrate to enable attachment to other devices. The solder balls may preferably have a diameter between about 8 and 20 mils. The chip may preferably have a thickness between about 10 and 20 mils. In one embodiment, potting material encapsulates the chip adding a thickness of about 6 mils. The substrate may preferably have a thickness between about 8 and 28 mils. In a single layer embodiment, the substrate has a thickness of about 12 mils.
In a multi-layer embodiment, the integrated circuit package of the present invention has bus bars and routing strips are disposed adjacent to the openings of the substrate. The first layer may have a thickness of about 12 mils and a second layer may have a thickness of about 8 mils. Alternatively, a first layer may have a thickness of about 12 mils, a second layer may have a thickness of about 8 mils and a third layer may have a thickness of about 8 mils. The profile of the integrated circuit package of the present invention may preferably be between about 30 mils and 50 mils.